This invention relates to an improved shift circuit which shifts data at a high speed.
FIG. 1 is a schematic block circuit diagram of a central processing unit 2 (hereinafter called "CPU 2"). The CPU 2 is a single chip circuit comprising temporary registers (A, T, B, M) 4, an arithmetic logic circuit 8, a shifter 10, a microprogram ROM 12, a branch control unit 14, a status control unit 16, a common bus buffer/receiver 18, a timing generator & bus controller 22, and a special function unit 26.
The temporary registers 4 store data supplied through an internal bus 6. The arithmetic logic unit 8 carries out arithmetic logic operations such as addition, subtraction, AND, OR with respect to data set from the temporary registers 4. The shifter 10 is designed to shift the data sent from the temporary registers 4. The microprogram ROM 12 stores information showing the sequence in which data are processed by the CPU 2. The branch control unit 14 controls the branching of a microprogram. The status control unit 16 includes flip-flop registers for storing the current status of the CPU 2 and a circuit for controlling the status of the flip-flop registers. The common bus buffer/receiver 18 receives and supplies data through an external bus. The timing generator & bus controller 22 controls transmission of data between the CPU 2 and a memory means or an input-output device and produces clock signals for defining the timing in which data are stored into the temporary registers 4 and general registers. The special function unit 26 is used to, for example, expand a bit arrangement.
The shifter 10 is a conventional shift register. It shifts a 1-bit data at one cycle. Thus, to shift an m-bit data it would take m-cycle time. To shorten the time necessary for shifting data a new type of computer has been developed which has a shifter for shifting data at a high speed. Such a shifter is shown in FIG. 2.
FIG. 2 is a block circuit diagram of a shifter consisting of a plurality of data selectors (DS) which are cascade-connected. The shifter receives an n-bit input data (n=8) and shifts the data by m-bit positions (m&lt;n) at one cycle. To the shifter an 8-bit data is supplied through input lines 28, a 3-bit data specifying an amount of shifting (i.e. m) is supplied through first control lines 30, and a 1-bit data specifying a "right" or "left" shift is supplied through a second control line 32. Both the 3-bit data and the 1-bit data are supplied to the data selectors DS. If the 1-bit data specifies "right" shift, the 8-bit data is shifted to the right by m bits and is obtained through output lines 34 at one cycle. If the 1-bit specifies "left" shift, the 8-bit data is shifted to the left by m bits and is obtained through output lines 36 at one cycle.
With the shifter shown in FIG. 2, however, several steps must be carried out, as will be described below, in order to shift a multi-length data (2n bits, 3n bits, . . . ) by m bits either to the right or to the left.